1. Field of the Invention
The present invention is generally directed to voltage regulator circuits. More specifically, the present invention is directed to pulse-width modulated current mode controllers in switching regulators which commonly utilize leading edge blanking circuitry.
2. Background
Conventional current mode control circuits result in unique waveforms which can interfere with proper regulation of the output voltage in switching power supplies. A typical current mode control circuit commonly used in switching power supplies is represented by the block diagram circuit of FIG. 1A. In general, sensed current through an inductive load coupled to a power transistor is used for current mode control and cycle-by-cycle current limiting. The current mode control circuit has a voltage feedback loop 100 and a current-sense feedback loop 102 which work together to provide a regulated output voltage at V.sub.out 104. However, a gate charge current pulse (I.sub.charge) 142 alters the leading edge of a current-sense waveform causing erroneous response in the peak current sensing feedback control circuitry and interferes with the proper regulation of the output voltage V.sub.out 104.
In the example current mode control circuit of FIG. 1A, the voltage and current-sense feedback loops 100, 102 control the pulse width of the gate drive voltage pulse V.sub.g 106 which opens and closes the power transistor main switch 108. The main switch 108 is typically a MOSFET switch that, in conjunction with inductor 103, facilitates the transfer of energy from the voltage input V.sub.cc 110 to the voltage output V.sub.out 104 by opening and closing in response to the drive pulse V.sub.g 106. The width of each drive pulse V.sub.g 106 is regulated by feedback through the voltage and current-sense feedback loops 100, 102 and determines the length of time during each clock cycle that the main switch 108 remains closed in order to build up energy in the inductor L 103. The longer the switch 108 is closed, the larger the transferred energy, resulting in a larger voltage output V.sub.out 104. Conversely, a shorter conduction interval of switch 108 results in a lower voltage output V.sub.out 104. The drive pulse V.sub.g 106 is generated by a constant-frequency clock 112 driving a latch 114. The output voltage V.sub.out 104 is thus regulated by the constant-frequency, pulse-width modulated voltage pulse V.sub.g 106.
In operation, the voltage and current-sense feedback loops 100, 102 modulate the width of the drive pulse V.sub.g 106 by continually monitoring the output voltage V.sub.out 104 and sensing the current flowing through the main switch 108. In the example current mode control circuit of FIG. 1A, 5 volts has been chosen as a typical value for V.sub.out 104. Resistors R1116 and R2118 make up a voltage divider which divides down V.sub.out 104 to provide a V.sub.error 120 voltage which is continually monitored within the voltage feedback loop 100. A voltage reference V.sub.ref 122 is set such that V.sub.error 120 is equal to V.sub.ref 122 when V.sub.out 104 is properly regulated to 5 volts. A typical value for V.sub.ref 122 is 1.25 volts, and thus the resistors R1116 and R2118 are selected to provide a value of 1.25 volts at V.sub.error 120 for a properly regulated V.sub.out 104 value of 5 volts. Any change in voltage at V.sub.out 104 results in a corresponding change in V.sub.error 120. The voltage difference between V.sub.error 120 and V.sub.ref 122 is then amplified by the error amplifier 124, resulting in an adjustment of the error amplifier 124 output voltage level V.sub.ea 126. During each clock cycle, a current-sense comparator 128 compares V.sub.ea 126 with the current-sense voltage V.sub.s 130, which is the voltage across a current-sense resistor R.sub.s 132 that rises as current flows through the closed main switch 108. The current-sense voltage V.sub.s 130 tracks the linearly increasing current through inductor L 103, and thus the energy being transferred from the voltage input V.sub.cc 110 to the voltage output V.sub.out 104, during each clock cycle as the main switch 108 is in a closed position due to the gate drive pulse V.sub.g 106. During each clock cycle, the gate drive pulse V.sub.g 106 keeps the main switch 108 closed until the current-sense voltage V.sub.s 130 rises to the level of V.sub.ea 126, at which point the current-sense comparator 128 resets the R-S flip-flop 114 which terminates the gate drive pulse V.sub.g 106 and opens the main switch 108 until the next clock cycle begins. Thus, the current-sense comparator 128 uses the monitored output voltage V.sub.out 104 and the sensed current through inductor L 103 to modulate the width of the drive pulse V.sub.g 106 and regulate V.sub.out 104.
The operation of the current mode control circuit of FIG. 1A is more readily understood with reference to the clock pulse 112, the gate drive pulse V.sub.g 106 and the voltage V.sub.s 130 waveforms as shown in FIG. 1B. The gate drive pulse V.sub.g 106 begins with each clock pulse 112 and acts to close the main switch 108, causing a linear rise in current through inductor L 103 and a corresponding rise in the current-sense voltage V.sub.s 130 across the current-sense resistor R.sub.s 132. When V.sub.s 130 rises to the level pre-set by error amplifier 124 output voltage V.sub.ea 126, the current-sense comparator 128 resets the R-S flip-flop 114, terminating the gate drive pulse V.sub.g 106 which opens the main switch 108 and causes resistor R.sub.s 132 to pull V.sub.s 130 to ground until the next clock cycle begins.
A change in the error amplifier 124 output voltage V.sub.ea 126, as shown for example by V.sub.ea2 136 in FIG. 1B, is the result of the voltage feedback loop 100 of FIG. 1A responding to a drop in the output voltage V.sub.out 104. As is apparent from the V.sub.s2 131 waveform of FIG. 1B, a drop in the output voltage V.sub.out 104 results in a widening of the gate drive pulse V.sub.g 106 holding the main switch 108 closed, since V.sub.s2 131 must rise to a higher level in order to reach V.sub.ea2 136 and cause comparator 128 to reset the R-S flip-flop 114. Thus, the voltage and current-sense feedback loops 100, 102 work to correct the drop in output voltage V.sub.out 104 by holding the main switch 108 closed for a longer period of time during each clock cycle 112 so that more energy is transferred from the voltage input V.sub.cc 110 to the voltage output V.sub.out 104.
In addition to illustrating the operation of a typical current mode control circuit in a switching power supply, FIGS. 1A & 1B also illustrate the fundamental problem associated with using the current-sense voltage V.sub.s 130 waveform to control the complex current mode control circuitry. The current-sense voltage V.sub.s 130 waveform is not usable in its natural form to control the current mode control circuit because of the leading edge spike 138 which is apparent in the V.sub.s 130 waveform of FIGS. 1B & 2B. The partial circuit of FIG. 2A and accompanying waveforms of FIG. 2B illustrate how the gate drive pulse V.sub.g 106 is differentiated by a series connection of the the gate-source capacitance C.sub.gs 140 of the MOSFET switch 108 and the current-sense resistor R.sub.s 132 resulting in the leading edge spike 138. It is apparent from the waveforms of FIG. 2B that the leading edge spike 138 of the current-sense voltage V.sub.s 130 reaches its peak value at the same time that the gate charge current pulse I.sub.charge 142 (I.sub.charge path also illustrated in FIG. 1A) reaches its peak through the current-sense resistor R.sub.s 132 during the MOSFET switch 108 turn-on transition. Although several factors influence the leading edge spike 138 such as bias conditions in the driver circuitry 144, reverse recovery characteristics of the diode D1146, transformer parasitics and the Miller effect, the main source of the leading edge spike 138 is the gate-source capacitance C.sub.gs 140 of the MOSFET switch 108. The value of the leading edge spike 138 in the current-sense voltage V.sub.s 130 can be high enough to intersect the voltage V.sub.ea 126 and cause the current-sense comparator 128 to incorrectly shut down the gate drive pulse V.sub.g 106, resulting in inaccurate regulation of V.sub.out 104.
There are two basic solutions to this problem which both incorporate the use of leading edge blanking circuitry to blank out the leading edge spike 138. Approximately ninety percent of today's applications apply a frequency domain solution which utilizes a simple R-C low pass filter 300 as illustrated in FIG. 3A to remove the leading edge spike 138 from the current-sense voltage V.sub.s 130 waveform. The V.sub.s 130 waveform is illustrated in FIG. 3B both before 302 and after 304 the R-C filter 300. If a sufficient amount of filtering is applied, the leading edge spike 138 can be removed entirely. However, a fundamental problem with frequency domain leading edge blanking circuits is the difficulty in controlling the amplitude of the leading edge spike 138 with respect to the clock pulse 112 in the manufacturing process, which requires the designer to consider the worst case conditions in order to provide an adequate amount of filtering. Such a conservative design approach results in undesirably long propagation delay in the current-sense signal which is objectionable because it effects the control loop performance and adds to the reaction time of the cycle-by-cycle current limit circuits.
Another often used method to remove the leading edge spike 138 is a time domain solution which incorporates a series switch 400 in the current-sense feedback path as illustrated in FIG. 4A to interrupt the feedback signal prior to the arrival of the leading edge spike 138. After the leading edge spike 138 has passed, the switch 400 is closed to re-establish the feedback path. The V.sub.s 130 waveform is illustrated in FIG. 4B both before 402 and after 404 the blanking interval created by the switch 400. Although time domain leading edge blanking circuits are insensitive to magnitude variations in the leading edge spike 138, they are sensitive to the variations in its timing and width. If the leading edge spike 138 is wider than the blanking interval or if the blanking interval does not completely overlap the leading edge spike 138, full leading edge blanking cannot be achieved. Perfect synchronization of the blanking interval has been difficult to ensure in the prior art because of variations in propagation delays (td1 and td2 in FIG. 4A) in the manufacturing process. These variations and a further need to accommodate variations in the width of the leading edge spike 138 have required circuits in the prior art to be designed with an increased blanking interval. Such a conservative design approach results in undesirably long propagation delay in the current-sense signal which is objectionable because it effects the control loop performance and adds to the reaction time of the cycle-by-cycle current limit circuits.
Thus, leading edge blanking circuits in the prior art suffer disadvantages including a lack of proper alignment of the blanking interval with the leading edge spike, sensitivity to the leading edge spike width variations and sensitivity to the leading edge spike magnitude variations. Accordingly, there exists a need for a circuit which overcomes the disadvantages of circuits in the prior art in blanking out the leading edge spike in pulse width modulated current mode switching power supply controllers.